Position: Senior SoC Verification Engineer
Location: Sunnyvale/Mountain View


- Define and develop verification architecture, methodologies,
protocols and environments
- Write verification specifications, verification plans and
- Generate test benches and automatic regression plans
- Be responsible for verification architecture, simulations,
verifications and debugging of circuit and logic designs (schematics,
analog, RTL)
- Complete block-level verification and chip level verification
- Interface with cross-functional teams and collaborate in all
verification related activities

Required skills and Experience:
BSEE or MSEE (Preferred)
- Minimum of 8 years related silicon design or verification work
- Hands on full product cycle project experience architecting and
executing verification projects using OVM
- Hands on coverage driven verification project experience
- Hands on assertion based verification project experience
- Experience writing verification plans as well as test bench
development, simulation and debugging
- Knowledge of IC chip design, development flow, process, and
- Knowledge of CMOS logic design, circuit design, circuit analysis and
CMOS device operation and characteristics
- Proficient in HDL languages System Verilog, Verilog and VHDL
- Good knowledge of UNIX shell scripting, Perl and TCL scripting
- Proficiency in a UNIX environment and CAE/CAD tools such as schematic
capture, simulation, design verification
- Good analytical and problem solving skills

Contact Information:

Company is a leader in its space, working on leading edge technologies and
products, gaining market share, has $ in the bank!

Please send resume to zshuster AT batnet DOT com

Zig Shuster
zshuster AT batnet DOT com