Position: Senior Mask Design Engineer
Location: Milpitas, CA

Company:
In this position, the individual will be responsible for developing and preparing multi-dimensional layouts and detailed drawings of the semiconductor devices from schematics and related geometry provided by design engineering. The individual will also check dimensions, write specifications, and verify completed drawings, artwork or digitized plots. Lastly the individual may check design layouts and detailed drawings.

This position requires 5 - 9 years of good layout experience in memories, flash memory a plus, detailed exposure and experience with analog circuit layout, the ability to understand and build memory arrays and experience with laying out pitch circuits. The individual should have strong skills in floor-planning and manual routing, understand the routing and placement requirements based on schematics, experience in planning and routing power bus and full chip routing and experience with at least one chip from start to tape-out. Additional requirements include the ability to do complex standard cell and macro cell library layout including supporting engineers with developing flash memory specific library development, experience with layout of I/O circuits, including pad blocks, good understanding of ESD and latch-up requirements for layout, experience in understanding parasitics and its impact to layout, ability to optimize critical paths, proficiency in post layout processing,
preferably using Hercules tool set, ablity to learn and understand design rules very quickly, knowledge of Cadence opus layout and schematic tools and the ability to debug drc/lvs independently.

The individual should be able to understand schematics, schematic hierarchy and be able to plan and complete layout from schematics, should be proficient in understanding layout and schematic hierarchy of existing chips and be able to make changes to existing chips and be able to at least take ownership of parts of the full chip, needs to have good layout and layout planning skills and be able to provide quality layout without much supervision, experience with Cadence “VLE, VXL” layout tool, experience in Hercules DRC/LVS verification tool and the ability to develop standard cell and macro cell library for flash memory chips and analog circuit layout with focus on charge pump and voltage generator. The individual must also have experience with I/O blocks including pad block layout, cell-level, block-level and full chip level DRC/LVS and various post processing of layers required for flash memory chips, be able to take ownership of complex blocks of the chip; do the detailed planning based on requirements, complete floor-plan for the block, plan the routing and complete the routing (manually), support optimization of various blocks including routing and via optimization, support full chip activities including tape-out and ECO’s after initial tape-out and complete cell level and block level layout from schematics and work with various schematic hierarchy to determine proper layout hierarchy. Lastly the individual must be able to support pitch circuit layout such as x-decoder, sense-amp, y-path, work as part of a layout team; needs to be a team oriented person, support test structure development including structures necessary for design rule development and work closely with layout manager & layout project and interface with designers and CAD engineers when necessary

SanDisk offers a highly competitive compensation package and great benefits, which include Stock Options, ESPP, matched 401 (K), comprehensive insurance and tuition reimbursement. SanDisk is an equal opportunity employer.

Contact:
For immediate consideration, please submit your resume online to:
sjobs.brassring.com/1033/ASP/TG/cim_jobdetail.asp?partnerid=11730&siteid=111&AReq=5902BR&Codes=LINK