ASIC Validation Engineer

We are a fabless semiconductor company developing innovative, chip-based power management technologies that will improve the portability and integration of unplugged electronics. Our technology will enable a new generation of feature-rich, mobile electronic products while reducing part counts and lowering total costs to make systems that are smaller, lighter, more power efficient and affordable.

Position Description:
The ASIC Validation Engineer will participate in the validation of SoC’s in a mixed signal design environment. The candidate will generate test benches and run regression simulations to help verify that the design of the SoC is compliant to the product specifications. Documentation of test benches will be required.

Duties and Responsibilities:
-”Verification that chip design is compliant to the product specifications and models.

-”Generates and documents test bench specifications and test coverage metrics

-”Simulates designs containing RTL, behavioral, and mixed signal blocks

-”Will participate in full chip verification of mixed signal designs.

-”Work with design engineers to create and refine new functional blocks.

Required Skills:
-”5+ years IC design with SoC verification, module design, and DFT experience

-”Experience with IC design tools preferably NC-verilog, Ultrasim, C, PERL, Mentor DFT, and Verplex

-”Experience in SoC design with an understanding of Low Power design requirements.

-”Strong analytical skills

-”Excellent organizational, interpersonal and communication skills

-”BS (MS preferred) in Electrical Engineering, Computer Engineering, Computer Technology or equivalent

Desired Skills:
-”Experience in mixed-signal design and debug.

-”Understanding of low power design techniques such as clock gating and managing multiple on chip voltage domains.

Kate Hasterlik

Executive and Technical Placements

Tandem Recruiting Group

kate@tanrg.com

o/m:1-406-220-1411